Implementation of a Feature Point Stereo Image Matching Algorithm on a Transputer Network

This paper will focus on the issues concerned with a parallel implementation strategy for the feature point stereo image matching algorithm published by Barnard and Thompson (See Barnard and Thompson 1981). The performance and software engineering aspects of the implementation on a parallel computer are discussed. This implementation is expected to provide a foundation for one processing stage in the development of a Transputer-based system for real-time production of depth maps from a variety of data sources. The implementation strategy utilises the asyn-chronous SIMD mode of processing in which the same program is executed on each processor, but not in "lock-step". A simple framework has been devised that supports all necessary modes of interprocessor communication, and permits parameterisation of the logical and physcal configuration of the array. Preliminary results on speed will be given, and their effect on future implementation strategies discussed. In the real world, sensor geometry cannot be assumed to be epipolar e.g. SPOT (See Chevrel et al 1981, Dowman 1982). Barnard and Thompson's algorithm is capable of processing stereo imagery captured under such conditions, and generates a sparse disparity map which may be used to refine estimates for the relative orientation parameters of the sensor. The typical processing sequence in order to produce epipolar SPOT stereo pairs would be: 1. Input raw SPOT stereo pairs and platform parameters. 2. Calculate rough estimates of absolute orientation parameters. 3. Define overlapping areas of interest in stereo pair. 4. Apply Barnard and Thompson to rough epipo-lar SPOT stereo pair, to obtain a sparse disparity map. 5. Refine sparse disparity map to required accuracy for step 6 and 7. 6. Calculate resampling transformation required to 7. produce epipolar SPOT stereo pairs. Resample to epipolar. An adequate specification of the algorithm existed in the literature, permitting direct implementation in Oc-cam2, the target machine being a Meiko Computing Surface. This approach permitted the competence of the original algorithm and the speed of the parallel implementation to be assessed together. This is a useful approach: quality and speed metrics are dependent upon each other, and algorithm and implementation issues can be studied together rather than in isolation. Following this evaluation, recommmendations to improve both the com-petences and speed of the algorithm are to be made based upon the results to date.